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ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia2110803 14 - 13 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 1 of 85 1 - 888 - 824 - 4184 ia186eb/ia188eb 8 - bit/16 - bit microcontrollers data sheet
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia2110803 14 - 13 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 2 of 85 1 - 888 - 824 - 4184 copyright 2011 by innovasic semiconductor, inc. published by innovasic semiconductor, inc. 3737 princeton drive ne, suite 130, albuquerque, nm 8 7107 miles ? is a trademark innovasic semiconductor, inc. intel is a registered trademark of intel corporation
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 3 of 85 1 - 888 - 824 - 4184 table of contents 1. introduction ................................ ................................ ................................ ............................. 7 1.1 general descri ption ................................ ................................ ................................ ....... 7 1.2 features ................................ ................................ ................................ ......................... 8 2. packaging, pin descriptions, and physical dimensions ................................ ......................... 9 2.1 packages and pinouts ................................ ................................ ................................ .... 9 2.1.1 ia186eb 84 plcc package ................................ ................................ ........... 10 2.1.2 ia188eb 84 plcc package ................................ ................................ ........... 12 2.1.3 plcc physical dimensions ................................ ................................ ............ 14 2.1.4 ia186eb 80 pqfp package ................................ ................................ ........... 15 2.1.5 ia188eb 8 0 pqfp package ................................ ................................ ........... 17 2.1.6 pqfp physical dimensions ................................ ................................ ............ 19 2.1.7 ia186eb 80 lqfp package ................................ ................................ ........... 20 2.1.8 ia188eb 80 lqfp package ................................ ................................ ........... 22 2.1.9 lqfp physical dimensions ................................ ................................ ............ 24 2.2 ia186eb pin/signal descriptions ................................ ................................ ............... 25 2.3 ia188eb pin/signal descriptions ................................ ................................ ............... 34 3. maximum ratings, thermal characteristics, and dc parameters ................................ ....... 42 4. functional description ................................ ................................ ................................ .......... 44 4.1 device architecture ................................ ................................ ................................ ..... 44 4.1.1 bus interface unit ................................ ................................ ........................... 44 4.1.2 clock generator ................................ ................................ .............................. 46 4.1.3 interrupt control unit ................................ ................................ ..................... 47 4.1.4 timer /counter unit ................................ ................................ ........................ 47 4.1.5 serial communications unit ................................ ................................ ........... 47 4.1.6 chip - select unit ................................ ................................ ............................. 47 4.1.7 i/o port unit ................................ ................................ ................................ ... 48 4.1.8 refresh control unit ................................ ................................ ....................... 48 4.1.9 power management unit ................................ ................................ ................ 48 4.2 peripheral architecture ................................ ................................ ............................... 48 4.3 reference documents ................................ ................................ ................................ . 51 5. ac specifications ................................ ................................ ................................ ................. 51 5.1 ac test conditions ................................ ................................ ................................ ..... 55 5.2 clock input and clock output timing characteristics ................................ ............... 56 5.3 serial port mode 0 timing characteristics ................................ ................................ . 58 6. reset operation ................................ ................................ ................................ .................... 59 7. bus timing ................................ ................................ ................................ ........................... 59 8. instruction execution times ................................ ................................ ................................ . 69 9. errata ................................ ................................ ................................ ................................ ..... 77 9.1 summary ................................ ................................ ................................ ..................... 77 9.2 detail ................................ ................................ ................................ ........................... 78
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 4 of 85 1 - 888 - 824 - 4184 10. revision history ................................ ................................ ................................ ................... 83 11. for additional information ................................ ................................ ................................ ... 85
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 5 of 85 1 - 888 - 824 - 4184 list of figures figure 1 . ia186eb 84 - pin plcc package diagram ................................ ................................ .... 10 figure 2. ia188eb 84 - pin plcc package diagram ................................ ................................ .... 12 figure 3. 84 - pin plcc physical package dimensions ................................ ................................ 14 figure 4 . ia186eb 80 - pin pqfp pac kage diagram ................................ ................................ .... 15 figure 5 . ia188eb 80 - pin pqfp package diagram ................................ ................................ .... 17 figure 6. 80 - pin pqfp physical package dimensions ................................ ................................ . 19 figure 7 . ia186eb 80 - pin lqfp package diagram ................................ ................................ .... 20 figure 8 . ia188eb 80 - pin lqfp package diagram ................................ ................................ .... 22 figure 9. 80 - pin lqfp physical package dimensions ................................ ................................ . 24 figure 10. ia186eb/ia188eb functional block diagram ................................ .......................... 45 figure 11. clock circuit connection options ................................ ................................ .............. 46 figure 12. ac input characteristics ................................ ................................ ............................. 51 figure 13. ac output characte ristics ................................ ................................ ........................... 52 figure 14. relative timing characteristics ................................ ................................ .................. 54 figure 15. ac test load ................................ ................................ ................................ .............. 55 figure 16. clock input and clock output timing characteristics ................................ ............... 56 figure 17. serial port mode 0 timing characteristics ................................ ................................ . 58 figure 18. cold reset timing ................................ ................................ ................................ ....... 60 figure 19. warm reset timing ................................ ................................ ................................ .... 61 figure 20. read, fetch, and refresh cycle t iming ................................ ................................ ...... 62 figure 21. write cycle timing ................................ ................................ ................................ ..... 63 figure 22. halt cycle timing ................................ ................................ ................................ ....... 64 figure 23. interrupt acknowledge (inta1_n, inta0_n) cycle timing ................................ ........... 65 figure 24. hold/hlda timing ................................ ................................ ................................ ......... 66 figure 25. ref resh during hold acknowledge timing ................................ ............................... 67 figure 26. ready timing ................................ ................................ ................................ .............. 68
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 6 of 85 1 - 888 - 824 - 4184 list of tables table 1. ia186eb 84 - pin plcc pin listing ................................ ................................ ................ 11 table 2. ia188eb 84 - pin plcc pin listing ................................ ................................ ................ 13 table 3. ia186eb 80 - pin pqfp pin listing ................................ ................................ ................ 16 table 4. ia188eb 80 - pin pqfp pin listing ................................ ................................ ................ 18 table 5. ia186eb 80 - pin lqfp pin listing ................................ ................................ ................ 21 table 6. ia188eb 80 - pin lqfp pin listing ................................ ................................ ................ 23 table 7. ia186eb pin/signal descriptions ................................ ................................ .................. 25 table 8. ia188eb pin/signal descriptions ................................ ................................ .................. 34 table 9. ia186eb and ia188eb absolute maximum ratings ................................ .................... 42 ta ble 10. ia186eb and ia188eb thermal characteristics ................................ ......................... 42 table 11. ia186eb and ia188eb dc parameters ................................ ................................ ....... 43 table 12. peripheral co ntrol block registers ................................ ................................ .............. 49 table 13. ac input characteristics for 5.0 - volt operation ................................ .......................... 52 table 14. ac input characteristics for 3 .3 - volt operation ................................ .......................... 52 table 15. ac output characteristics for 5.0 - volt operation ................................ ....................... 53 table 16. ac output characteristics for 3.3 - volt operation ................................ ....................... 53 table 17. relative timing characteristics ................................ ................................ .................... 55 table 18. clock input and clock output timing characteristics for 5.0 - volt operation ........... 56 table 19. clock input and output characteristics for 3.3 - volt operation ................................ ... 57 table 20. serial port mod e 0 timing characteristics ................................ ................................ ... 58 table 21. instruction set timing ................................ ................................ ................................ .. 69 table 22. innovasic part number cross - reference for the plcc ................................ ............... 74 table 23. innovasic part number cross - reference for the pqfp ................................ ................ 75 table 24. innovasic part number cross - reference for the lq fp ................................ ............... 76 table 25. summary of errata ................................ ................................ ................................ ........ 77 table 26. revision history ................................ ................................ ................................ ........... 83
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 7 of 85 1 - 888 - 824 - 4184 1. introduction the innovasi c semiconductor ia186eb and ia188eb microcontrollers are form, fit, and function replacements for the original intel ? 80c186eb, 80c188eb, 80l186eb, and 80l188eb 16 - bit high - integration embedded processors. these devices are produced using innovasics manag ed ic lifetime extension system (miles?). this cloning technology, which produces replacement ics beyond simple emulations, ensures complete compatibility with the original device, including any Dundocumented features. additionally, the miles process ca ptures the clone design in such a way that production of the clone can continue even as silicon technology advances. the ia186eb and ia188eb microcontrollers replace the obsolete intel 80c186eb and 80c188eb devices, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts. 1.1 general description the innovasic semiconductor ia186eb and ia188eb microcontrollers are an upgrade for the 80c186eb/ 80c188eb microcontroller designs with integrated peripherals to provide increased functionality and reduce system costs. the ia186eb and ia188eb devices are designed to satisfy requirements of embedded products designed for telecommunications, office automation and storage, and industria l controls. the ia186eb and ia188eb microcontrollers have a set of base peripherals beneficial to many embedded applications and include a standard numeric interface, an interrupt control unit, a chip - select unit, a dram refresh control unit, a power manag ement unit, and three 16 - bit timer/counters. the ia186eb and ia188eb microcontrollers are capable of operating at 5.0 or 3.3 volts. this datasheet discusses both modes of operation. where applicable, characteristics specific to either 3.3 or 5.0 volt ope ration are identified separately throughout this datasheet. additionally, the ia186eb and ia188eb include two integrated serial ports that support both synchronous and asynchronous communications, simplifying inter - processor and display communications. th e ia186eb and ia188eb also have an enhanced chip - select unit and two multiplexed i/o ports. the enhanced chip - select unit offers 10 general chip selects, each with the ability to address up to 1 m byte. this enhanced unit enables memory - bank switching to expand the ia186eb/i a1 88eb 1 mbyte address space. the i/o ports allow for basic functions such as scanning keypads for input. the ports can also be used to control system power consumption, disabling unneeded components. the serial ports, i/o capabilitie s, and enhanced chip selects make the ia186eb/ia188eb an excellent processor for portable data acquisition or communication applications.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 8 of 85 1 - 888 - 824 - 4184 1.2 features the primary features of the ia186eb and ia188eb microcontrollers are as follows: low - power operating modes C id le (freezes cpu clocks; peripherals are kept active) C power - down (freezes all internal clocks) low - power cpu core (static) direct addressing capability C memory: 1 mbyte C i/o: 64 kbyte i/o ports C 2 ea ch , 8 - bit C multiplexed clock generator chip selects C 10 ea ch , programmable C integral wait - state generator memory refresh control unit interrupt controller, programmable counter/timers C 3 ea ch , 16 - bit C programmable serial channels C 2 ea ch , uarts C integral baud rate generator operating frequency (system clock input) C 50 mhz @ 5v C 32 mhz @ 3 .3v chapter 4, functional description , provides detail s of the ia186eb and ia188eb microcontrollers, including the features listed above.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 9 of 85 1 - 888 - 824 - 4184 2. packaging , pin descriptions , and physical dimensions info rmation on the packages and pin descriptions for the ia186eb and the ia188eb is provided separately. r efer to sections, figures, and tables for information on the device of interest. 2.1 packages and pinouts the innovasic semiconductor ia186eb and ia188 eb mic rocontroller is available in the following packages: 84 - pin plastic leaded chip carrier (plcc) , equivalent to original plcc package 80 - pin plastic quad flat pack ( p qfp) , equivalent to original pqfp package 80 - pin low - profile quad flat pack (lqfp) , equivale nt to original sqfp package
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 10 of 85 1 - 888 - 824 - 4184 2.1.1 ia186eb 84 plcc package the pinout for the ia186eb 84 plcc package is as shown in figure 1 . the corresponding pinout is provided in table 1 . figure 1 . ia186eb 84 - pin plcc package diagram
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 11 of 85 1 - 888 - 824 - 4184 table 1 . ia186eb 84 - pin plcc pin listing pin name pin name pin name pin name 1 v cc 22 v ss 43 v ss 64 v cc 2 v ss 23 v cc 44 clkout 65 v ss 3 error_n 24 p1.4/gcs4 _n 45 t0out 66 ad1 4 rd_n 25 p1.3/gcs3_n 46 t0in 67 ad9 5 wr_n 26 p1.2/gcs2_n 47 t1out 68 ad2 6 ale 27 p1.1/gcs1_n 48 t1in 69 ad10 7 bhe_n 28 p1.0/gcs0_n 49 p2.7 70 ad3 8 s2_n 29 lcs_n 50 p2.6 71 ad11 9 s1_n 30 ucs_n 51 cts0_n 72 ad4 10 s0_n 31 int0 52 txd0 73 ad12 11 den_n 32 int1 53 rxd0 7 4 ad5 12 hlda 33 int2/inta0_n 54 p2.5/bclk0 75 ad13 13 hold 34 int3/inta1_n 55 p2.3/sint1 76 ad6 14 test_n/busy 35 int4 56 p2.4/cts1_n 77 ad14 15 lock_n 36 pdtmr 57 p2.0/rxd1 78 ad7 16 dt/r_n 37 resin_n 58 p2.1/txd1 79 ad15 17 nmi 38 resout 59 p2.2/bclk1 80 a16 18 ready 39 pereq 60 ncs_n 81 a17 19 p1.7/gcs7_n 40 oscout 61 ad0 82 a18 20 p1.6/gcs6_n 41 clkin 62 ad8 83 a19/once_n 21 p1.5/gcs5_n 42 v cc 63 v ss 84 v ss
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 12 of 85 1 - 888 - 824 - 4184 2.1.2 ia188 eb 84 plcc package the pinout for the ia188 eb 8 4 plcc package is as shown in figure 2 . the corresponding pinout is provided in table 2 . figure 2 . ia188eb 84 - pin plcc package diagram
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 13 of 85 1 - 888 - 824 - 4184 table 2 . ia188eb 84 - pin plcc pin listing pin name pin name pin n ame pin name 1 v cc 22 v ss 43 v ss 64 v cc 2 v ss 23 v cc 44 clkout 65 v ss 3 not connected 24 p1.4/gcs4 _n 45 t0out 66 ad1 4 rd_n 25 p1.3/gcs3_n 46 t0in 67 a9 5 wr_n 26 p1.2/gcs2_n 47 t1out 68 ad2 6 ale 27 p1.1/gcs1_n 48 t1in 69 a10 7 r fsh_n 28 p1.0/gcs0_n 49 p2.7 70 ad3 8 s2_n 29 lcs_n 50 p2.6 71 a11 9 s1_n 30 ucs_n 51 cts0_n 72 ad4 10 s0_n 31 int0 52 txd0 73 a12 11 den_n 32 int1 53 rxd0 74 ad5 12 hlda 33 int2/inta0_n 54 p2.5/bclk0 75 a13 13 hold 34 int3/inta1_n 55 p2.3/sint1 76 ad6 14 test_n 35 int4 56 p2.4/cts1_n 77 a14 15 lock_n 36 pdtmr 57 p2.0/rxd1 78 ad7 16 dt/r_n 37 resin_n 58 p2.1/txd1 79 a15 17 nmi 38 resout 59 p2.2/bclk1 80 a16 18 ready 39 not connected 60 not connected 81 a17 19 p1.7/gcs7_n 40 oscout 61 ad0 82 a18 20 p1.6/gcs6_n 41 clkin 62 a8 83 a19/once_n 21 p1.5/gcs5_n 42 v cc 63 v ss 84 v ss
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 14 of 85 1 - 888 - 824 - 4184 2.1.3 plcc physical dimensions the physical dimensions for the 84 plcc are as shown in figure 3 . legend: figure 3 . 84 - pin plcc physical package dimensions symbol min nom max a 0 .165 ? C 0.180 ? a1 0.090 ? C 0.120 ? d C 1.190 ? C d1 C 1.154 ? C e C 1.190 ? C e1 C 1.154 ? C f C 1.110 ? C f1 C 1.110 ? C note : the bottom package is bigger than the top package by 0.004 inches (0.002 inches per side). bottom package dimension s follow th os e stated in this drawing.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 15 of 85 1 - 888 - 824 - 4184 2.1.4 ia186 eb 80 pqfp pa c kage the pinout for the ia 186 eb 80 pqfp package is as shown in figure 4 . the corresponding pinout is provided in table 3 . figure 4 . ia186eb 80 - pin p qfp package diagram
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 16 of 85 1 - 888 - 824 - 4184 table 3 . ia186eb 80 - pin p qfp pin listing pin name pin na me pin name pin name 1 cts0_n 21 ad4 41 s1_n 61 ucs_n 2 txd0 22 ad12 42 s0_n 62 int0 3 rxd0 23 ad5 43 den_n 63 int1 4 p2.5/bclk0 24 ad13 44 hlda 64 int2/inta0_n 5 p2.3/sint1 25 ad6 45 hold 65 int3/inta1_n 6 p2.4/cts1_n 26 ad14 46 t est_n 66 int4 7 p2.0/rxd1 27 ad7 47 lock_n 67 pdtmr 8 p2.1/txd1 28 ad15 48 nmi 68 resin_n 9 p2.2/bclk1 29 a16 49 ready 69 resout 10 ad0 30 a17 50 p1.7/gcs7_n 70 oscout 11 ad8 31 a18 51 p1.6/gcs6_n 71 clkin 12 vss 32 a19/once_n 52 p1 .5/gcs5_n 72 vcc 13 vcc 33 vss 53 vss 73 vss 14 vss 34 vcc 54 vcc 74 clkout 15 ad1 35 vss 55 p1.4/gcs4_n 75 t0out 16 ad9 36 rd_n 56 p1.3/gcs3_n 76 t0in 17 ad2 37 wr_n 57 p1.2/gcs2_n 77 t1out 18 ad10 38 ale 58 p1.1/gcs1_n 78 t1in 1 9 ad3 39 bhe_n 59 p1.0/gcs0_n 79 p2.7 20 ad11 40 s2_n 60 lcs_n 80 p2.6
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 17 of 85 1 - 888 - 824 - 4184 2.1.5 ia188 eb 80 pqfp package the pinout for the ia188 eb 80 pqfp package is as shown in figure 5 . the corresponding pinout is provided in table 4 . figure 5 . ia188 eb 80 - pin pqfp package diagram
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 18 of 85 1 - 888 - 824 - 4184 table 4 . ia188eb 80 - pin pqfp pin listing pin name pin name pin name pin name 1 cts0_n 21 ad4 41 s1_n 61 ucs_n 2 txd0 22 a12 42 s0_n 62 int0 3 rxd0 23 ad5 43 den_n 63 int1 4 p2.5/bclk0 24 a13 44 hlda 64 int2/inta0_n 5 p2.3/sint1 25 ad6 45 hold 65 int3/inta1_n 6 p2.4/cts1_n 26 a14 46 test_n 66 int4 7 p2.0/rxd1 27 ad7 47 lock_n 67 pdtmr 8 p2.1/txd1 28 a15 48 nmi 68 resin_n 9 p2.2/bclk1 29 a16 49 ready 69 resout 10 ad0 30 a17 50 p1.7/gcs7_n 70 oscout 11 a8 31 a18 51 p1.6/gcs6_n 71 clkin 12 vss 32 a19/once_n 52 p1.5/gcs5_n 72 vcc 13 vcc 33 vss 53 vss 73 vss 14 vss 34 vcc 54 vcc 74 clkout 15 ad1 35 vss 55 p1.4/gcs4_n 75 t0out 16 a9 36 rd_n 56 p1.3/gcs3_n 76 t0in 17 ad2 37 wr_n 57 p1.2/gcs2_n 77 t1out 18 a10 38 ale 58 p 1.1/gcs1_n 78 t1in 19 ad3 39 rfsh_n 59 p1.0/gcs0_n 79 p2.7 20 a11 40 s2_n 60 lcs_n 80 p2.6
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 19 of 85 1 - 888 - 824 - 4184 2.1.6 pqfp physical dimensions the physical dimensions for the 80 pqfp are as shown in figure 6 . figure 6 . 80 - pin pqfp physical package dimensions legend: symbol millimeter inch min nom max min nom max a C C 3.40 C C 0.134 a1 0.25 C C 0.010 C C a2 2.55 2.72 3.05 0.100 0.107 0.120 d 23.90 basic 0.941 basic d1 20.00 basic 0.787 basic e 17.90 basic 0.705 ba sic e1 14.00 basic 0.551 basic r2 0.013 C 0.30 0.005 C 0.012 r1 0.013 C C 0.005 C C 0 3.5 7 0 3.5 7 1 0 C C 0 C C 2, 3 a 7 ref 7 ref 2, 3 b 15 ref 15 ref c 0.11 0.15 0.23 0.004 0.006 0.009 l 0.73 0.88 1.03 0.029 0.035 0.041 l1 1. 95 ref 0.077 ref s 0.40 C C 0.016 C C b 0.30 0.35 0.45 0.012 0.014 0.018 e 0.80 bsc 0.031 bsc d2 18.40 ref 0.724 e2 12.00 ref 0.472 tolerances of form and position aaa 0.25 0.010 bbb 0.20 0.008 ccc 0.20 0.008 a alloy 42 l/f. b copper l/f. notes : 1. dimension d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. dimension d1 and e1 do not include mold mismatch an d are determined a datum plane C h C . 2. dimension b does not include dambar protrusion. allowable dambar protrusion will not cau se the lead width to exceed the maximum b dimension by more than 0.08mm. dambar cannot be located on the lower radius of the lead foot.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 20 of 85 1 - 888 - 824 - 4184 2.1.7 ia186 eb 80 lqfp package the pinout for the ia186 eb 80 lqfp package is as shown in figure 7 . the corresponding pinout is provided in table 5 . figure 7 . ia186eb 80 - pin lqfp package diagram
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 21 of 85 1 - 888 - 824 - 4184 table 5 . ia186eb 80 - pin l qfp pin listing pin name pin name pin name pin name 1 hlda 21 int2/inta 0_n 41 p2.5/bclk0 61 ad13 2 hold 22 int3/inta1_n 42 p2. 3/sint1 62 ad6 3 test_n 23 int4 43 p2.4/cts1_n 63 ad14 4 lock_n 24 pdtmr 44 p2.0/rxd1 64 ad7 5 nmi 25 resin_n 45 p2.1/txd1 65 ad15 6 ready 26 resout 46 p2.2/bclk1 66 a16 7 p1.7/gcs7_n 27 oscout 47 ad0 67 a17 8 p1.6/gcs6_n 28 clkin 4 8 ad8 68 a18 9 p1.5/gcs5_n 29 v cc 49 v ss 69 a19/once_n 10 v ss 30 v ss 50 v cc 70 v ss 11 v cc 31 clkout 51 v ss 71 v cc 12 p1.4/gcs4_n 32 t0out 52 ad1 72 v ss 13 p1.3/gcs3_n 33 t0in 53 ad9 73 rd_n 14 p1.2/gcs2_n 34 t1out 54 ad2 74 wr_n 1 5 p1.1/gcs1_n 35 t1in 55 ad10 75 ale 16 p1.0/gcs0_n 36 p2.7 56 ad3 76 bhe_n 17 lcs_n 37 p2.6 57 ad11 77 s2_n 18 ucs_n 38 cts0_n 58 ad4 78 s1_n 19 int0 39 txd0 59 ad12 79 s0_n 20 int1 40 rxd0 60 ad5 80 den_n
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 22 of 85 1 - 888 - 824 - 4184 2.1.8 ia188 eb 80 lqfp package the pinout for the ia188 eb 80 lqfp package is as shown in figure 8 . the corresponding pinout is provided in table 6 . figure 8 . ia188 eb 80 - pin lqfp package diagram
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 13 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 23 of 85 1 - 888 - 824 - 4184 table 6 . ia188eb 80 - pin lqfp pin li sting pin name pin name pin name pin name 1 hlda 21 int2/inta 0_n 41 p2.5/bclk0 61 a13 2 hold 22 int3/inta1_n 42 p2.3/sint1 62 ad6 3 test_n 23 int4 43 p2.4/cts1_n 63 a14 4 lock_n 24 pdtmr 44 p2.0/rxd1 64 ad7 5 nmi 25 resin_n 45 p2.1/tx d1 65 a15 6 ready 26 resout 46 p2.2/bclk1 66 a16 7 p1.7/gcs7_n 27 oscout 47 ad0 67 a17 8 p1.6/gcs6_n 28 clkin 48 a8 68 a18 9 p1.5/gcs5_n 29 v cc 49 v ss 69 a19/once_n 10 v ss 30 v ss 50 v cc 70 v ss 11 v cc 31 clkout 51 v ss 71 v cc 12 p1. 4/gcs4_n 32 t0out 52 ad1 72 v ss 13 p1.3/gcs3_n 33 t0in 53 a9 73 rd_n 14 p1.2/gcs2_n 34 t1out 54 ad2 74 wr_n 15 p1.1/gcs1_n 35 t1in 55 a10 75 ale 16 p1.0/gcs0_n 36 p2.7 56 ad3 76 rfsh _n 17 lcs_n 37 p2.6 57 a11 77 s2_n 18 ucs_n 38 ct s0_n 58 ad4 78 s1_n 19 int0 39 txd0 59 a12 79 s0_n 20 int1 40 rxd0 60 ad5 80 den_n
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 24 of 85 1 - 888 - 824 - 4184 2.1.9 lqfp physical dimensions the physical dimensions for the 80 lqfp are as shown in figure 9 . figure 9 . 80 - pin lqfp physical package dimensions legend: symbol dimension in mm dimension in inch min nom max m in mom max a C C 1.60 C C 0.063 a 1 0.05 C 0.15 0.002 C 0.006 a 2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 b 1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.09 C 0.20 0.004 C 0.008 c 1 0.09 C 0.16 0.004 C 0.006 d 14.00 bsc 0.551 bsc d 1 12.00 bsc 0.472 bsc e 14.00 bsc 0.551 bsc e 1 12.00 bsc 0.472 bsc e 0.50 bsc 0.020 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l 1 1.00 ref 0.039 ref r 1 0.08 C C 0.003 C C r 2 0.08 C 0.20 0.003 C 0.008 s 0.20 C C 0.008 C C 0 3.5 7 0 3.5 7 1 0 C C 0 C C 2 11 12 13 11 12 13 3 11 12 13 11 12 13 notes : 1 . exact shape of each corner is optional . 2 . control ling dimension: mm. 1. to be determined at seating plane c. 2. dimensions d1 and e1 do not include mold protrusion. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. dimension b does not include dambar protrusion. dambar cannot be located on the lower radius of the foot. 4. exact shape of each corner is optional. 5. these dimensions apply to the flat se ction of the lead between 0.10 and 0.25mm from the lead tip. 6. a1 is defined as the distance from the seating plane to the lowest point of the package body.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 25 of 85 1 - 888 - 824 - 4184 2.2 ia186eb pin/signal descriptions descriptions of the pin and signal functions for t he ia186eb microcontroller are provided in table 7 . several of the ia186eb pins have different functions depending on the operating mode of the device. each of the different signals supported by a pin is listed and defined in table 7 indexed alphabeticall y in the first column of the table. additionally, the name of the pin associated with the signal as well as the pin numbers for the plcc, lqfp, and pqfp packages are provided in the Dpin column. signals not used in a specific package type are designated Dna . table 7 . ia186eb pin/signal descriptions signal pin description name plcc l qfp p qfp a16 (output only) a16 80 66 29 a ddress bits [ 16 C 19 ] . input/output . these pins provide the four most - significant bits of the address bu s. during the address portion of the ia186eb bus cycle, address bits [ 16 C 19 ] are presented on the bus and can be latched using the ale signal (see table entry). during the data portion of the ia186eb bus cycle, these lines are driven to a logic 0. a17 (output only) a17 81 67 30 a18 (output only) a18 82 68 31 a19 a19 /once_n 83 69 32 ad0 ad0 61 47 10 a ddress/ d ata bits [ 0 C 15 ] . input/output. these pins provide the multiplexed address bus and data bus. during the address portion of the ia186eb bus cycle, address bits [ 0 C 15 ] are presented on the bus and can be latched using the ale signal (see next table entry). during the data portion of the ia186eb bus cycle, 8 - or 16 - bit data are present on these lines. ad1 ad1 66 52 15 ad2 ad2 68 54 17 ad3 ad3 70 56 19 ad4 ad4 72 58 21 ad5 ad5 74 60 23 ad6 ad6 76 62 25 ad7 ad7 78 64 27 ad8 ad8 62 48 11 ad9 ad9 67 53 16 ad10 ad10 69 55 18 ad11 ad11 71 57 20 ad12 ad12 73 59 22 ad13 ad13 75 61 24 ad14 ad14 77 63 26 ad15 ad15 79 65 28
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 26 of 85 1 - 888 - 824 - 4184 table 7 . ia186eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp ale ale 6 75 38 a ddress l atch e nable. output. active high. this signal is used to latch the address information during the address portion of a bus cycl e. bclk0 p2.5/ bclk0 54 41 4 b aud cl oc k , serial port 0 . input. the bclk0 pin can be used to provide an alternate clock source for serial port 0. the input clock rate cannot be greater than one - half the operating frequency of the ia186eb. bclk1 p2.2/ bcl k1 59 46 9 b aud cl oc k , serial port 1 . input. the bclk1 pin can be used to provide an alternate clock source for serial port 1. the input clock rate cannot be greater than one - half the operating frequency of the ia186eb. bhe_n bhe_n is multi - plexed with refresh_n bhe_n bhe_n is multi - plexed with refresh_n 7 76 39 b yte h igh e nable. output. active low. when bhe_n is asserted (low), it indicates that the bus cycle in progress is transferring data over the upper half of the data bus. additionally , bhe_n and ad0 encode the following bus information: ad0 bhe_n bus status 0 0 word transfer 0 1 even byte transfer 1 0 odd byte transfer 1 1 refresh operation note: bhe_n is multiplexed with refresh_n . busy test_n/ busy 14 na na busy . input. act ive high. when the busy input is asserted, it causes the ia186eb to suspend operation during the execution of the intel 80c187 numerics coprocessor instructions. operation resumes when the pin is sampled low. this applies to the plcc package only.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 27 of 85 1 - 888 - 824 - 4184 tabl e 7 . ia186eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp clkin clkin 41 28 71 cl oc k in put. input. the clkin pin is the input connection for an external clock. an external oscillator operating at two times the requ ired processor operating frequency can be connected to this pin. if a crystal is used to supply the clock, it is connected between the clkin pin and the oscout pin (see oscout table entry). when a crystal is connected, it drives a n internal pierce oscill ator to the ia186eb. clkout clkout 44 31 74 cl oc k out put. output. the clkout pin provides a timing reference for inputs and outputs of the ia186eb. this clock output is one - half the input clock ( clkin ) frequency. the clkout signal has a 50% duty cycle , transitioning every falling edge of clkin . cts0_n cts0_n 51 38 1 c lear t o s end, serial port 0 . input. active low. when this input is high (i.e., not asserted), data transmission from serial port 0 is inhibited. when the signal is asserted (low), dat a transmission is permitted. cts1_n p2.4/ cts1_n 56 43 6 c lear t o s end, serial port 1 . input. active low. when this input is high (i.e., not asserted), data transmission from serial port 1 is inhibited. when the signal is asserted (low), data transmiss ion is permitted. den_n den_n 11 80 43 d ata e n able. output. active low. this signal is used to enable of bidirectional transceivers in a buffered system. the den_n signal is asserted (low) only when data is to be transferred on the bus. dt/r_n dt/r_n 16 na na d ata t ransmit/ r eceive. output. this signal is used to control the direction of data flow for bidirectional buffers in a buffered system. when dt/r_n is high, the direction indicated is transmit; when dt/t_n is low, the direction indicated is r eceive. error_n error_n 3 na na error . input. active low. when this signal is asserted (low), it indicates that the last numerics coprocessor operation resulted in an exception condition.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 28 of 85 1 - 888 - 824 - 4184 table 7 . ia186eb pin/signal descriptions (continued) signal p in description name plcc l qfp p qfp gcs0_n p1.0/ gcs0_n 28 16 59 g eneric c hip s elect n ( n = 0 C 7). output. active low. when programmed and enabled, each of these pins provide a chip select signal that will be asserted (low) whenever the address of a me mory or i/o bus cycle is within the address space programmed for that output. gcs1_n p1.1/ gcs1_n 27 15 58 gcs2_n p1.2/ gcs2_n 26 14 57 gcs3_n p1.3/ gcs3_n 25 13 56 gcs4_n p1.4/ gcs4_n 24 12 55 gcs5_n p1.5/ gcs5_n 21 9 52 gcs6_n p1.6/ gcs6_n 20 8 51 gcs7_n p1.7/ gcs7_n 19 7 50 hlda hlda 12 1 44 h o ld a cknowledge. output. active high. when hlda is asserted (high), it indicates that the ia186eb has relinquished control of the local bus to another bus master in response to a hold request (see next ta ble entry). when hlda is asserted, the ia186eb data bus and control signals float , allowing another bus master to drive the signals directly. hold hold 13 2 45 hold . input. active high. this signal is a request indicating that an external bus master w ishes to gain control of the local bus. the ia186eb will relinquish control of the local bus between instruction boundaries not conditioned by a lock prefix. int0 (input) int0 (input only ) 31 19 62 interrupt n ( n = 0 - 4). input/output. active high. th ese maskable inputs interrupt program flow and cause execution to continue at an interrupt vector of a specific interrupt type as follows: int0 : type 12 int1 : type 13 int2 : type 14 int3 : type 15 int4 : type 17 to allow interrupt expansion, int0 and i nt1 can be used with the interrupt acknowledge signals inta0_n and inta1_n (see next table entries) to serve as external interrupt inputs or interrupt acknowledge outputs. int1 (input) int1 (input only ) 32 20 63 int2 int2 /inta0_n 33 21 64 int3 int3 /in ta1_n 34 22 65 int4 (input) int4 (input only ) 35 23 66 inta0_n int2/ inta0_n 33 21 64 int errupt a cknowledge 0 . input/output. active low. this pin provides an interrupt acknowledge handshake in response to an interrupt request on the int0 pin (see pre vious table entry).
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 29 of 85 1 - 888 - 824 - 4184 table 7 . ia186eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp inta1_n int3/ inta1_n 34 22 65 int errupt a cknowledge 1 . input/output. active low. this pin provides an interrupt acknowledge handsh ake in response to an interrupt request on the int1 pin (see previous table entry). lcs_n lcs_n 29 17 60 l ower c hip s elect. output. active low. this pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycl e is within the address space programmed for that output. lock_n lock_n 15 4 47 lock . output. active low. when asserted (low), this signal indicates that the bus cycle in progress is cannot be interrupted. while lock_n is active, the ia186eb will not service bus requests such as hold. ncs_n ncs_n 60 na na n umerics c oprocessor s elect. output. active low. this signal is asserted (low) when the ia186eb accesses an intel 80c187 numerics coprocessor. nmi nmi 17 5 48 n on - m askable i nterrupt. input. a ctive high. when the nmi signal is asserted (high) it causes a type 2 interrupt to be serviced by the ia186eb. note : the assertion of nmi is latched internally by the ia186eb. once_n a19/ once_n 83 69 32 on - c ircuit e mulation. input. active low. note : once mode is used for device testing. if the once_n pin is driven low during a reset operation, all ia186eb output and input/output pins are placed in a high - impedance state. this pin is weakly held high while resin_n is active.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 30 of 85 1 - 888 - 824 - 4184 table 7 . ia186eb pin /signal descriptions (continued) signal pin description name plcc l qfp p qfp oscout oscout 40 27 70 osc illator out put. output. the oscout pin is the output connection for an external crystal that drives the ia186eb internal pierce oscillator. (when a n external crystal is used, it is connected between this pin and the clkin pin . s ee clkin table entry.) note : if an external oscillator or clock source is used to drive the ia186eb instead of a crystal, oscout must be left unconnected (i.e., must float) . when the ia186eb is operating in the once mode, oscout does not float. p1.0 p1.0 /gcs0_n 28 16 59 p ort 1 , bit [ n ] (n = 0 C 7 ). output. each pin of port 1, p1.0 C p1.7 , can function individually as a general - purpose output line. p1.1 p1.1 /gcs1_n 27 15 58 p1.2 p1.2 /gcs2_n 26 14 57 p1.3 p1.3 /gcs3_n 25 13 56 p1.4 p1.4 /gcs4_n 24 12 55 p1.5 p1.5 /gcs5_n 21 9 52 p1.6 p1.6 /gcs6_n 20 8 51 p1.7 p1.7 /gcs7_n 19 7 50 p2.0 p2.0 /rxd1 57 44 7 p ort 2 , bit [ 0 ] . input /output . this pin functions as a general - p urpose i/o line. p2.1 p2.1 /txd1 58 45 8 p ort 2 , bit [ 1 ] . output. this pin functions as a general - purpose output line. p2.2 p2.2 /bclk1 59 46 9 p ort 2 , bit [ 2 ] . input. this pin functions as a general - purpose input line. p2.3 p2.3 /sint1 55 42 5 p ort 2 , bit [ 3 ] . output. t his pin functions as a general - purpose output line. p2.4 p2.4 /cts1_n 56 43 6 p ort 2 , bit [ 4 ] . input. this pin functions as a general - purpose input line. p2.5 p2.5 /bclk0 54 41 4 p ort 2 , bit [ 5 ] . input. this pin functions as a gene ral - purpose input line. p2.6 p2.6 50 37 80 p ort 2 , bit [ 6 ] . input/output (open drain). this pin functions as a general - purpose bidirectional input/output line. p2.7 p2.7 49 36 79 p ort 2 , bit [ 7 ] . input/output (open drain). this pin functions as a gen eral - purpose bidirectional input/output line.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 31 of 85 1 - 888 - 824 - 4184 table 7 . ia186eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp pdtmr pdtmr 36 24 67 p ower - d own t i m e r . input/output (push - pull). note : the ia186eb enters powerdown mode when the pwrdn bit in the power control register is set to 1 and a halt instruction is executed. exit from the powerdown mode occurs upon receipt of a non - maskable interrupt (i.e., assertion of the nmi input) or a reset (i.e., assertion of the resin_n in put). the pdtmr pin, which is normally connected to an external capacitor, determines the amount of time that the ia186eb waits before resuming normal operation after an exit from the powerdown when a non - maskable interrupt is received essentially a delay between the assertion of the nmi input and the enabling of the ia186eb internal clocks. the delay required depends on the start - up characteristics of the crystal oscillator. the pdtmr pin does not apply when the powerdown mode is exited by the receipt o f a reset (i.e., the assertion resin_n ). pereq pereq 39 na na numerics co p rocessor e xternal req uest. input. active high. when asserted (high), this signal indicates that a data transfer between an intel 80c187 numerics coprocessor.and memory is pending . this applies to the plcc only. rd_n rd_n 4 73 36 r ea d . output. active low. when asserted (low), rd_n indicates that the accessed memory or i/o device must drive data from the location being accessed onto the data bus. ready ready 18 6 49 ready . inp ut. active high. when asse r ted (high) the ready line indi cates a bus - cycle completion. this signal must be active to terminate any bus cycle unless the ia186eb chip - select unit is configured to ignore ready . resin_n resin_n 37 25 68 res et in put. input . active low. when resin_n is asserted (low), the ia186eb immediately terminates any bus cycle in progress and assumes an initialized state. all pins are driven to a known state, and resout (see next table entry) is asserted.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 32 of 85 1 - 888 - 824 - 4184 table 7 . ia186eb pin/sig nal descriptions (continued) signal pin description name plcc l qfp p qfp resout resout 38 26 69 res et out put. output. active high. when resout is asserted, it indicates that the ia186eb is being reset. the resout signal will remain active (high) as long as resin_n remains active (low). rxd0 rxd0 53 40 3 receive ( rx ) d ata, serial port 0 . input/output. this pin is the serial data input for serial port 0. during synchronous serial communications, rxd0 is bidirectional and functions an output for data transmission ( txd0 becomes the clock). rxd1 p2.0/ rxd1 57 44 7 receive ( rx ) d ata, serial port 1 . input/output. this pin is the serial data input for serial port 1. during synchronous serial communications, rxd 1 is bidirectional and functions an output f or data transmission ( txd 1 becomes the clock). s0_n s0_n 10 79 42 s tatus n ( n = 0 C 2). output. during a bus cycle the status (i.e., type) of cycle is encoded on these lines as follows: s2_n s1_n s0_n bus cycle status 0 0 0 interrupt acknowledge 0 0 1 r ead i/o 0 1 0 write i/o 0 1 1 processor halt 1 0 0 queue instruction fetch 1 0 1 read memory 1 1 0 write memory 1 1 1 no bus activity s1_n s1_n 9 78 41 s2_n s2_n 8 77 40 sint1 p2.3/ sint1 55 42 5 s erial int errupt, serial port 1 . output. active high . when sint1 is asserted (high), it indicates that serial port 1 requires service. t0in t0in 46 33 76 t imer 0 in put. input. depending on the timer mode programmed for timer 0, this input is used either as clock input or a control signal. t0out t0out 4 5 32 75 t imer 0 out put. output. depending on the timer mode programmed for timer 0, this output can provide a single clock or a continuous waveform. t1in t1in 48 35 78 t imer 1 in put. input. depending on the timer mode programmed for timer 1, this inpu t is used either as clock input or a control signal.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 33 of 85 1 - 888 - 824 - 4184 table 7 . ia186eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp t1out t1out 47 34 77 t imer 1 out put. output. depending on the timer mode programmed for timer 1, t his output can provide a single clock or a continuous waveform. test_n test_n /busy 14 3 46 test . i nput. active low. when the test_n input is high (i.e., not asserted), it causes the ia186eb to suspend operation during the execution of the wait instruct ion. operation resumes when the pin is sampled low (asserted). txd0 txd0 52 39 2 transmit ( tx ) d ata, serial port 0 . output. this pin is the serial data output for serial port 0. during synchronous serial communications, txd0 becomes the transmit clock ( rxd0 functions as an output for data transmission). txd1 p2.1/ txd1 58 45 8 transmit ( tx ) d ata, serial port 1 . output. this pin is the serial data output for serial port 1. during synchronous serial communications, txd 1 becomes the transmit clock ( rxd 1 functions as an output for data transmission). ucs_n ucs_n 30 18 61 u pper c hip s elect. output. active low. this pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the address space progr ammed for that output. v cc v cc 1, 23, 42, 64 11, 29, 50, 71 13, 34, 54, 72 power ( v cc ). this pin provides power for the ia186eb device. it must be connected to a +5v dc power source. v ss v ss 2, 22, 43, 63, 65, 84 10, 30, 49, 51, 70, 72 12, 14, 33, 35, 53, 73 ground ( v ss ). this pin provides the digital ground (0v) for the ia186eb. it must be connected to a v ss board plane. wr_n wr_n 5 74 37 wr ite . output. active low. when asserted (low), wr_n indicates that data available on the data bus are to be latched into the accessed memory or i/o device.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 34 of 85 1 - 888 - 824 - 4184 2.3 ia188eb pin/signal descriptions descriptions of the pin and signal functions for the ia188eb microcontroller are provided in table 8 . several of the ia188eb pins have different functions depending on the o perating mode of the device. each of the different signals supported by a pin is listed and defined in table 8 indexed alphabetically in the first column of the table. additionally, the name of the pin associated with the signal as well as the pin number s for the plcc, lqfp, and lqfp packages are provided in the Dpin column. table 8 . ia188eb pin/signal descriptions signal pin description name plcc l qfp p qfp a8 a8 62 48 11 a ddress bits [ 8 - 19 ] . output. these pins provide t he 12 most - significant bits of the address bus. during the entire ia188eb bus cycle, address bits [ 8 C 19 ] are presented on the bus and can be latched using the ale signal (see table entry). a9 a9 67 53 16 a10 a10 69 55 18 a11 a11 71 57 20 a12 a12 73 59 22 a13 a13 75 61 24 a14 a14 77 63 26 a15 a15 79 65 28 a16 a16 80 66 29 a17 a17 81 67 30 a18 a18 82 68 31 a19 a19 /once_n 83 69 32 ad0 ad0 61 47 10 a ddress / d ata bits [ 0 C 7 ] . input/output. these pins provide a multiplexed address bus and data bus. during the address portion of the ia188eb bus cycle, address bits [ 0 C 7 ] are presented on the bus and can be latched using the ale signal (see next table entry). during the data portion of the ia188eb bus cycle, 8 - bit data are present on these l ines. ad1 ad1 66 52 15 ad2 ad2 68 54 17 ad3 ad3 70 56 19 ad4 ad4 72 58 21 ad5 ad5 74 60 23 ad6 ad6 76 62 25 ad7 ad7 78 64 27 ale ale 6 75 38 a ddress l atch e nable. output. active high. this signal is used to latch the address information d uring the address portion of a bus cycle. bclk0 p2.5/ bclk0 54 41 4 b aud cl oc k , serial port 0 . input. the bclk0 pin can be used to provide an alternate clock source for serial port 0. the input clock rate cannot be greater than one - half the operating f requency of the ia188eb.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 35 of 85 1 - 888 - 824 - 4184 table 8. ia188eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp bclk1 p2.2/ bclk1 59 46 9 b aud cl oc k , serial port 1 . input. the bclk1 pin can be used to provide an alternate clock source for serial port 1. the input clock rate cannot be greater than one - half the operating frequency of the ia188eb. clkin clkin 41 28 71 cl oc k in put. input. the clkin pin is the input connection for an external clock. an external oscillator, operating at two times the required processor operating frequency, can be connected to this pin. if a crystal is used to supply the clock, it is connected between the clkin pin and the oscout pin (see oscout table entry). when a crystal is connected, it drives a n interna l pierce oscillator to the ia188eb. clkout clkout 44 31 74 cl oc k out put. output. the clkout pin provides a timing reference for inputs and outputs of the ia188eb. this clock output is one - half the input clock ( clkin ) frequency. the clkout signal has a 50% duty cycle, transitioning every falling edge of clkin . cts0_n cts0_n 51 38 1 c lear t o s end, serial port 0 . input. active low. when this input is high (i.e., not asserted), data transmission from serial port 0 is inhibited. when the signal is asse rted (low), data transmission is permitted. cts1_n p2.4/ cts1_n 56 43 6 c lear t o s end, serial port 1 . input. active low. when this input is high (i.e., not asserted), data transmission from serial port 1 is inhibited. when the signal is asserted (low), data transmission is permitted. den_n den_n 11 80 43 d ata en able. output. active low. this signal is used to enable of bidirectional transceivers in a buffered system. the den_n signal is asserted (low) only when data are to be transferred on the bus . dt/r_n dt/r_n 16 na na d ata t ransmit /r eceive. output. this signal is used to control the direction of data flow for bidirectional buffers in a buffered system. when dt/r_n is high, the direction indicated is transmit; when dt/t_n is low, the directio n indicated is receive.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 36 of 85 1 - 888 - 824 - 4184 table 8. ia188eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp gcs0_n p1.0/ gcs0_n 28 16 59 g eneric c hip s elect n ( n = 0 C 7). output. active low. when programmed and enabled, each of these pi ns provide a chip select signal that will be asserted (low) whenever the address of a memory or i/o bus cycle is within the address space programmed for that output. gcs1_n p1.1/ gcs1_n 27 15 58 gcs2_n p1.2/ gcs2_n 26 14 57 gcs3_n p1.3/ gcs3_n 25 13 56 gcs4_n p1.4/ gcs4_n 24 12 55 gcs5_n p1.5/ gcs5_n 21 9 52 gcs6_n p1.6/ gcs6_n 20 8 51 gcs7_n p1.7/ gcs7_n 19 7 50 hlda hlda 12 1 44 h o ld a cknowledge. output. active high. when hlda is asserted (high), it indicates that the ia188eb has relinquished c ontrol of the local bus to another bus master in response to a hold request (see next table entry). when hlda is asserted, the ia188eb data bus and control signals are floated , allowing another bus master to drive the signals directly. hold (input) hold (input) 13 2 45 hold . input. active high. this signal is a request indicating that an external bus master wishes to gain control of the local bus. the ia188eb will relinquish control of the local bus between instruction boundaries not conditioned by a lock prefix. int0 (input) int0 (input only ) 31 19 62 int errupt n (n = 0 C 4 ). input/output. active high. these maskable inputs interrupt program flow and cause execution to continue at an interrupt vector of a specific interrupt type as follows: int0 : type 12 int1 : type 13 int2 : type 14 int3 : type 15 int4 : type 17 to allow interrupt expansion, int0 and int1 can be used with the interrupt acknowledge signals inta0_n and inta1_n (see next table entries) to serve as external interrupt inputs or interr upt acknowledge outputs. int1 (input) int1 (input only ) 32 20 63 int2 int2 /inta0_n 33 21 64 int3 int3 /inta1_n 34 22 65 int4 (input) int4 (input only ) 35 23 66 inta0_n int2/ inta0_n 33 21 64 int errupt a cknowledge 0 . output. active low. this pin provides an interrupt acknowledge handshake in response to an interrupt request on the int0 pin (see previous table entry).
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 37 of 85 1 - 888 - 824 - 4184 table 8. ia188eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp inta1_n int3/ inta1_n 34 22 65 int errupt a cknowledge 1 . input/output. active low. this pin provides an interrupt acknowledge handshake in response to an interrupt request on the int1 pin (see previous table entry). lcs_n lcs_n 29 17 60 l ower c hip s elect. input/output. active low. this pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the address space programmed for that output. lock_n lock_n 15 4 47 lock . output. active low. when asserted (low), this signal ind icates that the bus cycle in progress is cannot be interrupted. while lock_n is active, the ia188eb will not service bus requests such as hold. nmi nmi 17 5 48 n on - m askable i nterrupt. input. active high. when the nmi signal is asserted (high) , it ca uses a type 2 interrupt to be serviced by the ia188eb. note: the assertion of nmi is latched internally by the ia188eb. once_n a19/ once_n 83 69 32 on - c ircuit e mulation. input. active low. note: once mode is used for device testing. if the once_n pi n is driven low during reset, all ia188eb output and input/output pins are placed in a high - impedance state. this pin is weakly held high while resin_n is active. oscout oscout 40 27 70 osc illator out put. output. the oscout pin is the output connection for an external crystal that drives the ia188eb internal pierce oscillator. (when an external crystal is used, it is connected between this pin and the clkin pin see clkin table entry.) note: if an external oscillator or clock source is used to drive t he ia188eb instead of a crystal, oscout must be left unconnected (i.e., must float). when the ia188eb is operating in the once mode, oscout does not float.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 38 of 85 1 - 888 - 824 - 4184 table 8. ia188eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qf p p1.0 p1.0 / gcs0_n 28 16 59 p ort 1 , bit [ n ] (n = 0 C 7 ). output. each pin of port 1, p1.0 C p1.7 , can function individually as a general - purpose output line. p1.1 p1.1 / gcs1_n 27 15 58 p1.2 p1.2 / gcs2_n 26 14 57 p1.3 p1.3 / gcs3_n 25 13 56 p1.4 p1.4 / gcs 4_n 24 12 55 p1.5 p1.5 / gcs5_n 21 9 52 p1.6 p1.6 / gcs6_n 20 8 51 p1.7 p1.7 /gcs7_n 19 7 50 p2.0 p2.0 /rxd1 57 44 7 p ort 2 , bit [ 0 ] . input /output . this pin functions as a general - purpose i/o line. p2.1 p2.1 /txd1 58 45 8 p ort 2 , bit [ 1 ] . output. thi s pin functions as a general - purpose output line. p2.2 p2.2 /bclk1 59 46 9 p ort 2 , bit [ 2 ] . input. this pin functions as a general - purpose input line. p2.3 p2.3 /sint1 55 42 5 p ort 2 , bit [ 3 ] . output. this pin functions as a general - purpose output line . p2.4 p2.4 /cts1_n 56 43 6 p ort 2 , bit [ 4 ] . input. this pin functions as a general - purpose input line. p2.5 p2.5 /bclk0 54 41 4 p ort 2 , bit [ 5 ] . input. this pin functions as a general - purpose input line. p2.6 p2.6 50 37 80 p ort 2 , bit [ 6 ] . input/out put (open drain). this pin functions as a general - purpose bidirectional input/output line. p2.7 p2.7 49 36 79 p ort 2 , bit [ 7 ] . input/output (open drain). this pin functions as a general - purpose bidirectional input/output line.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 39 of 85 1 - 888 - 824 - 4184 table 8. ia188eb pin/s ignal descriptions (continued) signal pin description name plcc l qfp p qfp pdtmr pdtmr 36 24 67 p ower - d own t i m e r . input/output (push - pull). note: the ia188eb enters powerdown mode when the pwrdn bit in the power control register is set to 1 and a hal t instruction is executed. exit from the powerdown mode occurs upon receipt of a non - maskable interrupt (i.e., assertion of the nmi input) or a reset (i.e., assertion of the resin_n input). the pdtmr pin, which is normally connected to an external capaci tor, determines the amount of time that the ia188eb waits before resuming normal operation after an exit from the powerdown when a non - maskable interrupt is received essentially a delay between the assertion of the nmi input and the enabling of the ia188eb internal clocks. the delay required depends on the start - up characteristics of the crystal oscillator. the pdtmr pin does not apply when the powerdown mode is exited by the receipt of a reset (i.e., the assertion resin_n ). rd_n rd_n 4 73 36 r ea d . outp ut. active low. when asserted (low), rd_n indicates that the accessed memory or i/o device must drive data from the location being accessed onto the data bus. ready ready 18 6 49 ready . input. active high. when asse r ted (high) the ready line indicate s the completion of a bus cycle. this signal must be active to terminate any bus cycle unless the ia188eb chip - select unit is configured to ignore ready . resin_n resin_n 37 25 68 res et in put. input. active low. when resin_n is asserted (low), the ia18 8eb immediately terminates any bus cycle in progress and assumes an initialized state. all pins are driven to a known state, and resout (see next table entry) is asserted. resout resout 38 26 69 res et out put. output. active high. when resout is assert ed , it indicates that the ia188eb is being reset. the resout signal will remain active (high) as long as resin_n remains active (low). rfsh_n rfsh_n 7 76 39 r e f re sh . output. active low. when rfsh_n is asserted (low), it indicates that a refresh cycle is in progress.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 40 of 85 1 - 888 - 824 - 4184 table 8. ia188eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp rxd0 rxd0 53 40 3 receive ( rx ) d ata, serial port 0 . input/output. this pin is the serial data input for serial port 0. during synchron ous serial communications, rxd0 is bidirectional and functions an output for data transmission ( txd0 becomes the clock). rxd1 p2.0/ rxd1 57 44 7 receive ( rx ) d ata , serial port 1 . input/output. this pin is the serial data input for serial port 1. during synchronous serial communications, rxd 1 is bidirectional and functions an output for data transmission ( txd 1 becomes the clock). s0_n s0_n 10 79 42 s tatus n (n = 0 C 2). output. during a bus cycle the status (i.e., type) of cycle is encoded on these lines as follows: s2_n s1_n s0_n bus cycle status 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 processor halt 1 0 0 queue instruction fetch 1 0 1 read memory 1 1 0 write memory 1 1 1 no bus activity s1_n s1_n 9 78 41 s2_n s2_n 8 77 40 sint1 p2.3/ sint1 55 42 5 s erial int errupt, serial port 1 . output. active high. when sint1 is asserted (high), it indicates that serial port 1 requires service. t0in t0in 46 33 76 t imer 0 in put. input. depending on the timer mode programmed for timer 0, this input is used either as clock input or a control signal. t0out t0out 45 32 75 t imer 0 out put. output. depending on the timer mode programmed for timer 0, this output can provide a single clock or a continuous waveform. t1in t1in 48 35 78 t imer 1 in put. input. depending on the timer mode programmed for timer 1, this input is used either as clock input or a control signal. t1out t1out 47 34 77 t imer 1 out put. output. depending on the timer mode programmed for timer 1, this output ca n provide a single clock or a continuous waveform.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 41 of 85 1 - 888 - 824 - 4184 table 8. ia188eb pin/signal descriptions (continued) signal pin description name plcc l qfp p qfp test_n test_n 14 3 46 test . input. active low. when the test_n input is high (i.e., not asserted), it causes the ia188eb to suspend operation during the execution of the wait instruction. operation resumes when the pin is sampled low (asserted). txd0 txd0 52 39 2 transmit ( tx ) d ata, serial port 0 . output. this pin is the serial data output for seria l port 0. during synchronous serial communications, txd0 becomes the transmit clock ( rxd0 functions as an output for data transmission). txd1 p2.1/txd1 58 45 8 transmit ( tx ) d ata, serial port 1 . output. this pin is the serial data output for serial por t 1. during synchronous serial communications, txd 1 becomes the transmit clock ( rxd1 functions as an output for data transmission). ucs_n ucs_n 30 18 61 u pper c hip s elect. output. active low. this pin provides a chip select signal that will be asserte d (low) whenever the address of a memory bus cycle is within the address space programmed for that output. v cc v cc 1, 23, 42, 64 11, 29, 50, 71 13, 34, 54, 72 power ( v cc ). this pin provides power for the ia188eb device. it must be connected to a +5v dc power source. v ss v ss 2, 22, 43, 63, 65, 84 10, 30, 49, 51, 70, 72 12, 14, 33, 35, 53, 73 ground ( v ss ). this pin provides the digital ground (0v) for the ia188eb. it must be connected to a v ss board plane. wr_n wr_n 5 74 37 wr ite . output. active low. when asserted (low), wr_n indicates that data available on the data bus are to be latched into the accessed memory or i/o device.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 42 of 85 1 - 888 - 824 - 4184 3. maximum ratings, thermal characteristics, and dc parameters for the innovasic semiconductor ia186eb and ia188eb microcontr ollers, the absolute maximum ratings, thermal characteristics, and dc parameters are provided in tables 9 through 1 1 , respectively. table 9 . ia186eb and ia188eb absolute maximum ratings parameter rating storage temperature ? 40 c to + 125 c supply voltage with respect to v ss ?0. 3 v to +6. 0 v voltage on pins other than supply with respect to v ss ?0. 3 v to +(vcc + 0. 3 )v table 10 . ia186eb and ia188eb thermal characteristics symbol characteristic value u nits t a ambient temperature - 40 c to 85 c c p d power dissipation mhz icc v/1000 w ja 84 - pin plcc package 3 0.7 c/w 80 - pin p qfp package 4 6 80 - pin lqfp package 52 t j average junction temperature t a + (p d ja ) c
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 43 of 85 1 - 888 - 824 - 4184 table 11 . ia186eb and ia188eb dc parameters symbol parameter min max units notes 5.0v operation v cc supply voltage 4.5 5.5 v C 3.3v operation v cc supply voltage 3.0 3.6 v C v il input low voltage ?0. 3 0.3 v cc v input hysteresis on resin_n = 0.50v v ih in put high voltage 0.7 v cc v cc + 0. 3 v C v ol output low voltage vcc = 5.5v or 3.6v C 0 . 4 v i ol = 12 ma v oh output high voltage vcc = 4.5v / 3. 0 v 3.5/2.4 C v i oh = ? 12 ma i leak input leakage current for pins: ad15 C ad0, ad7 C ad0 (ia188eb), ready, hold, resin_ n; clkin, test_n, nmi, int4 C int0, t0in, t1in, rdx0, bclk0_n, cts0_n, rxd1, bclk1_n, cts1_n, p2.6, p2.7 C 1 a 0v v in v cc input leakage current for pins (@3.3v) : pereq + . 147 +.625 ma v in = v cc input leakage current for pins (@3.3v) : a19/once_n, a18 C a16, lock_n , error_n ? .147 ? .625 ma v in =0 v input leakage current for pins (@5v) : pereq + . 227 +.833 ma v in = v cc input leakage current for pins (@5v) : a19/once_n, a18 C a16, lock_n , error_n ? .227 ? .833 ma v in =0 v i lo output leakage current C 1 0 a 0.45 v out v cc i id supply current (idle) - @ 50 mhz C 90 ma C c in input pin capacitance 0 5 pf t f = 1 mhz c out output pin capacitance 0 5 pf t f = 1 mhz operating temperature is - 40c to +85c.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 44 of 85 1 - 888 - 824 - 4184 4. functional description 4.1 device architecture a rchitecturally, the ia186eb and ia188eb microcontrollers include the following functional modules: bus interface unit clock generator interrupt control unit timer/counter unit serial communications unit chip - select unit i/o port unit refresh control unit p ower management unit a functional block diagram of the ia186eb/ia188eb is shown in figure 10 . descriptions of the functional modules are provided in the following subsections. 4.1.1 bus interface unit the ia186eb/ia188eb bus controller that generates local bus control signals and uses a hold/hlda protocol to share the local bus with other bus masters. the bus controller generates 20 address bits, read and write control signals, and bus - cycle status information. a ready input is used to extend a bus cycle beyon d the minimum four clock cycles.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 45 of 85 1 - 888 - 824 - 4184 figure 10 . ia186eb/ia188eb functional block diagram 2
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 46 of 85 1 - 888 - 824 - 4184 4.1.2 clock generator the ia186eb/ia188eb uses an on - chip clock generator to supply internal and external clocks. the clock generator makes use of a crystal oscillator and includes a divide - by - two counter. figure 11 shows the various operating modes of the clock circuit. the clock circuit can use either a parallel resonant fun damental mode crystal network ( a) or a third - overtone mode crystal netw ork ( b), or it can be drive n by an external clock source ( c). the following parameters are recommended when choosing a crystal: temperature range C application specific C esr (equivalent series resistance): 40 max C c0 (shunt capacitance of crystal): 7.0 pf max C cl (load capacitance): 20 pf 2 pf C drive level: 1 mw max figure 11 . clock circuit connection options
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 47 of 85 1 - 888 - 824 - 4184 4.1.3 interrupt control unit the ia186eb/ia188eb can receive interrupts fr om a number of sources, both internal and external. the interrupt control unit serves to merge these requests on a priority basis, for individual service by the cpu. each interrupt source can be independently masked by the interrupt control unit (icu) or all interrupts can be globally masked by the cpu. internal interrupt sources include the timers and serial channel 0. external interrupt sources come from the five input pins int0 C int4. the nmi interrupt pin is not controlled by the icu and is passed directly to the cpu. although the timer and serial channel each have only one request input to the icu, separate vector types are generated to service individual interrupts within the timer and serial channel units. 4.1.4 timer/counter unit the ia186eb/ia188eb timer/counter unit (tcu) provides three 16 - bit programmable timers. two of these are highly flexible and are connected to external pins for control or clocking. a third timer is not connected to any external pins and can only be clocked internally. howe ver, it can be used to clock the other two timer channels. the tcu can be used to count external events, time external events, generate non - repetitive waveforms, and generate timed interrupts, etc. 4.1.5 serial communications unit the serial control unit (scu) of the ia186eb/ia188eb contains two independent channels. each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller ( channel 1 has an external interrupt pin). each channel has its own baud rate generator that is independent of the timer/counter unit, and can be internally or externally clocked at up to one half the ia186eb/ia188eb operating frequency. independent baud rate generators are provided for each of the serial channels. for the asynchro nous modes, the generator supplies an 8x baud clock to both the receive and transmit register logic. a 1x baud clock is provided in the synchronous mode. 4.1.6 chip - select unit the ia186eb/ia188eb chip - select unit (csu) integrates logic that provides up to ten programmable chip - selects to access both memories and peripherals. in addition, each chip select can be programmed to automatically insert additional clocks (wait - states) into the current bus cycle and automatically terminate a bus cycle independent of th e condition of the ready input pin.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 48 of 85 1 - 888 - 824 - 4184 4.1.7 i/o port unit the i/o port unit (ipu) on the ia186eb/ia188eb supports two 8 - bit channels of input, output, or input/output operation. port 1 is multiplexed with the chip select pins and is output only. most of port 2 i s multiplexe d with the serial channel pins. 4.1.8 refresh control unit the refresh control unit (rcu) automatically generates a pe riodic memory read bus cycle to keep dynamic or pseudo - static memory refreshed. a 9 - bit counte r controls the number of clocks betwe en refresh requests. a 12 - bit address generator is maintained by the rcu and is presented on the a1 C a12 address lines during the refresh bus cycle. address bits [ a13 C a19 ] are programmable to allow the refresh address block to be located on any 8 - kbyte bou ndary. 4.1.9 power management unit the ia186eb/ia188eb power management unit (pmu) i s provided to control the power consumption of the device. the pmu provides three powe r modes: active, idle, and powerdown. active mode indicates that all units on the ia186eb/i a188eb are functional and the device consumes maximum power (depending on the level of peripheral operation). idle mode freezes the clocks of the execution and bus units at a logic zero state (all peripherals continue to operate normally). the powerdown m ode freezes all internal clocks at a logic zero level and disables the crystal oscillator. all internal registers hold their values provided v cc is maintained. cur rent consumption is reduced to just transistor junction leakage. 4.2 peripheral architecture th e ia186eb/ia188eb has integrated several common system peripherals with a cpu core to create a compact, yet powerful system. the integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e.g., the in terrupt control unit supports interrupt requests from the timer/counters or serial channels). the list of integrated peripherals includes: 7 - input interrupt control unit 3 - channel timer/counter unit 2 - channel serial communications unit 10 - output chip - sele ct unit i/o port unit refresh control unit
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 49 of 85 1 - 888 - 824 - 4184 power management unit the registers associated with each integrated peripheral are contained within a 128 16 register file called the peripheral control block (pcb). t he pcb can be located in either memory or i /o space on any 256 - byte address boundary. table 1 2 provides a list of the registers associated with the pcb. table 12 . peripheral control block registers pcb offset function pcb offset function pcb offset function pcb offset function 00h reserved 40h timer2 count 80h gcs0 start c0h reserved 02h end of interrupt 42h timer2 compare 82h gcs0 stop c2h reserved 04h poll 44h reserved 84h gcs1 start c4h reserved 06h poll status 46h timer2 control 86h gcs1 stop c6h res erved 08h interrupt mask 48h reserved 88h gcs2 start c8h reserved 0ah priority mask 4ah reserved 8ah gcs2 stop cah reserved 0ch in - service 4ch reserved 8ch gcs3 start cch reserved 0eh interrupt request 4eh reserved 8eh gcs3 stop ceh reserve d 10h interrupt status 50h port 1 direction 90h gcs4 start d0h reserved 12h timer control 52h port 1 pin 92h gcs4 stop d2h reserved 14h serial control 54h port 1 control 94h gcs5 start d4h reserved 16h int4 control 56h port 1 latch 96h gcs5 stop d6h reserved 18h int0 control 58h port 2 direction 98h gcs6 start d8h reserved 1ah int1 control 5ah port 2 pin 9ah gcs6 stop dah reserved 1ch int2 control 5ch port 2 control 9ch gcs7 start dch reserved 1eh int3 control 5eh port 2 latch 9eh gcs7 stop deh reserved
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 50 of 85 1 - 888 - 824 - 4184 table 1 2 . peripheral control block registers (continued) pcb offset function pcb offset function pcb offset function pcb offset function 20h reserved 60h serial0 baud a0h lcs start e0h reserved 22h reserved 62h seri al0 count a2h lcs stop e2h reserved pcb offset offset pcb offset function pcb offset function pcb offset function 24h reserved 64h serial0 control a4h ucs start e4h reserved 26h reserved 66h serial0 status a6h ucs stop e6h reserved 28h reser ved 68h serial0 rbuf a8h relocation e8h reserved 2ah reserved 6ah serial0 tbuf aah reserved eah reserved 2ch reserved 6ch reserved ach reserved ech reserved 2eh reserved 6eh reserved aeh reserved eeh reserved 30h timer0 count 70h serial1 b aud b0h refresh base f0h reserved 32h timer0 compare a 72h serial1 count b2h refresh time f2h reserved 34h timer0 compare b 74h serial1 control b4h refresh control f4h reserved 36h timer0 control 76h serial1 status b6h refresh address f6h res erved 38h timer1 count 78h serial1 rbuf b8h power control f8h reserved 3ah timer1 compare a 7ah serial1 tbuf bah reserved fah reserved 3ch timer1 compare b 7ch reserved bch step id 1 fch reserved 3eh timer1 control 7eh reserved beh reserved feh reserved note: 1 the step id register (offset 0xbc) for revision 2 of the innovasic device is read - only, and is uniquely identified in software by having a value of 0x0080. the original intel device established a value between 0x0000 and 0x0002, depen ding on the revision of the part.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 51 of 85 1 - 888 - 824 - 4184 4.3 reference documents additional information on the operation and programming of the 80c186eb/80c188eb can be found in the following intel publications: 80c186eb/80c188eb and 80l186eb/80l188eb 16 - bit high - integration embe dded processors (272433 - 006) 80c186eb/80c188eb microprocessor users manual (270830 - 00n) 5. ac specifications th is chapter defines the ac specifications of the ia186eb/ia188eb . input characteristics are provided in figure 12 and tables 13 and 14 . o utput ch aracteristics are provided in figure 1 3 and tables 15 and 1 6 . relative timing characteristics are provided in figure 1 4 and table 1 7 . clock input and clock output timing characteristics are provided in figure 18 and tables 18 and 19 . additional timing i nformation is provided in chapter 7, bus timing , and chapter 8, instruction execution times . the following test conditions were used to derive the values in tables 13 C 16: rev . 0 was tested at 100c and 4.75v; rev. 2 was tested at 100c and 4.5v. figure 12 . ac input characteristics clkout 50% valid t chih min min t chis valid t clih min min t clis
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 52 of 85 1 - 888 - 824 - 4184 for specific 5.0 - and 3.3 - volt characteristics, refer to tables 1 3 and 1 4 , respectively. table 13 . ac input characteristics for 5.0 - volt operation symbol pins min max units t chis test_n, nmi, int4 C int0, bclk1 C bclk0, t1in C t0in, ready, cts1_n C cts0_n, p2.6, p2.7 10 C ns t chih test_n, nmi, int4 C int0, bclk1 C bclk0, t1in C t0in, ready, cts1_n C cts0_n 3 C ns t clis ad15 C ad0, ad7 C ad0 (ia188eb), ready 10 C ns t clis hold, pereq, error_n 10 C ns t clih ad15 C ad0, ad7 C ad0 (ia188eb), ready 3 C ns t clih hold, pereq, error_n 3 C ns table 14 . ac input characteristics for 3.3 - volt operati on symbol pins min max units t chis test_n, nmi, int4 C int0, bclk1 C bclk0, t1in C t0in, ready, cts1_n C cts0_n, p2.6, p2.7 10 C ns t chih test_n, nmi, int4 C int0, bclk1 C bclk0, t1in C t0in, ready, cts1_n C cts0_n 3 C ns t clis ad15 C ad0, ad7 C ad0 (ia188eb), ready 10 C n s t clis hold, pereq, error_n 10 C ns t clih ad15 C ad0, ad7 C ad0 (ia188eb), ready 3 C ns t clih hold, pereq, error_n 3 C ns figure 13 . ac output characteristics for specific 5.0 - and 3.3 - volt characteristics, refer to tables 15 and 16, respectively.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 53 of 85 1 - 888 - 824 - 4184 table 15 . ac output characteristics for 5.0 - volt operation symbol parameter min ma x uni ts t chov ale, s2 C s0_n, den_n, dt/r_n, bhe_n, rfsh_n (ia188eb ), lock_n, a19 C a16 3 17 ns gcs0 C gcs7_n, lcs_n, ucs_n, nc s_n, rd_n, wr_n 3 20 ns t clov bhe_n, rfsh_n (ia188eb), den_n, lock_n, resout, hlda, t0out, t1out, a19 C a16 3 17 ns rd_n , wr_n, gcs7 C gcs0_n, lcs_n, ucs_n, ad15 C ad0, ad7 C ad0 (ia188eb), a15 C a8 (ia188eb), ncs_n, inta1_n C inta0_n, s2_n C s0_n 3 20 ns t chof re_ n, wr_n, bhe_n, rfsh_n (ia188eb), dt/r_n, lock_n, s2_n C s0_n, a19 C a16 0 20 ns t clof den_n, ad15 C ad0, ad7 C ad0 (ia188eb), a15 C a8 (ia188eb) 0 20 ns table 16 . ac output characteristics for 3.3 - volt operation symbol parameter min max units t chov ale, s2 C s0_n, den_n, dt/r_n, bhe_n, rfsh_n (ia188eb), lock_n, a19 C a16 3 25 ns gcs0 C gcs7_n, lcs_n, ucs_n, ncs_n, rd_n, wr_n 3 30 ns t clov bhe_n, rfsh_n (ia188eb), den_n, lock_n, resout, hlda, t0out, t1out, a19 C a16 3 25 ns rd_n , wr_n, gcs 7 C gcs0_n, lcs_n, ucs_n, ad15 C ad0, ad7 C ad0 (ia188eb), a15 C a8 (ia188eb), ncs_n, inta1_n C inta0_n, s2_n C s0_n 3 30 ns t chof re_n, wr_n, bhe_n, rfsh_n (ia188eb), dt/r_n, lock_n, s2_n C s0_n, a19 C a16 0 30 ns t clof den_n, ad15 C ad0, ad7 C ad0 (ia188eb), a15 C a8 (ia188 eb) 0 30 ns
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 54 of 85 1 - 888 - 824 - 4184 figure 14 . relative timing characteristics for specific relative timing characteristics, refer to table 17.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 55 of 85 1 - 888 - 824 - 4184 table 17 . relative timing characteristics symbol parameter min max units t lh ll ale rising to ale falling t C 15 C ns t avll address valid to ale falling ?t C 10 C ns t plll chip selects valid to ale falling ?t C 10 C ns t llax address hold from ale falling ?t C 10 C ns t llwl ale falling to wr_n falling ?t C 15 C ns t llrl ale falling to rd_n falling ?t C 15 C ns t whlh wr_n rising to ale rising ?t C 10 C ns t afrl address float to rd_n falling 0 C ns t rlrh rd_n falling to rd_n rising (2t) C 5 C ns t wlwh wr_n falling to wr_n rising (2t) C 5 C ns t rhav rd_n rising to address active t C 15 C ns t whdx output data hold after wr_n rising t C 15 C ns t whph wr_n rising to chip select rising ?t C 10 C ns t rhph rd_n rising to chip select rising ?t C 10 C ns t phpl cs_n inactive to cs_n active ?t C 10 C ns t ovrh once_n active to resin_n rising t C ns t rhox once_n hold to resin_n rising t C ns 5.1 ac test conditions the ac specifications are tested with the 50 - pf load shown in figure 15 . specifications are measured at the v cc /2 crossing point unless otherwise specified. figure 15 . ac test load
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 56 of 85 1 - 888 - 824 - 4184 5.2 clock input and clock output timing characteristics for clock input and clock output timing characteristics for both 5.0 - and 3.3 - volt operation , see tables 18 and 19 , respectively . figure 16 . cl ock input and clock output timing characteristics table 18 . clock input and clock output timing characteristics for 5.0 - volt operation item symbol parameter min max units notes C xtf clkin frequency 0 50 mhz C 1 tckin clkin peri od 20 ns C 2 tchck clkin high time 10 ns measure for vih for high time, nil for low time. 3 tclck clkin low time 10 ns measure for vih for high time, nil for low time. 4 tcklh clkin rise time 1 5 ns only required to guarantee icc. maximum limits are bounded for tc, tch , and tcl. 5 tckhl clkin fall time 1 5 ns only required to guarantee icc. maximum limits are bounded for tc, tch , and tcl. 6 tcico clkin to clkout delay 0 11.5 ns specified for a 50 - pf load . 7 tclcl clkout period C 2 tckin ns C 8 tchcl clkout high time (t clcl /2) C 5 ( tclcl /2) + 5 ns measure for vih for high time, nil for low time. 9 tccch clkout low time ( tclcl /2) C 5 ( tclcl /2) + 5 ns measure for vih for high time, nil for low time. 10 tch1ch2 clkout rise time 1 6 ns specified for a 50 - pf load . 11 tcl2cl1 clkout fall time 1 6 ns specified for a 50 - pf load .
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 57 of 85 1 - 888 - 824 - 4184 table 19 . clock input and output characteristics for 3.3 - volt operation item symbol parameter min max units notes C xtf clkin frequen cy 0 32 mhz C 1 tc clkin period 30 ns C 2 tch clkin high time 15 ns measure for vih for high time, nil for low time. 3 tcl clkin low time 15 ns measure for vih for high time, nil for low time. 4 tcr clkin rise time 1 5 ns only required to guarantee icc. maximum limits are bo unded for tc, tch and tcl. 5 tcf clkin fall time 1 5 ns only required to guarantee icc. maximum limits are bounded for tc, tch and tcl. 6 xtcd clkin to clkout delay 0 14.5 ns specified for a 50 - pf load . 7 t clk out period C 2tc ns C 8 tph clk ou t high time (t/2) C 5 (t/2) + 5 ns measure for vih for high time, nil for low time. 9 tpl clk out low time (t/2) C 5 (t/2) + 5 ns measure for vih for high time, nil for low time. 10 tpr clk out rise time 1 6 ns specified for a 50 - pf load . 11 tpf cl k out fall time 1 6 ns specified for a 50 - pf load .
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 58 of 85 1 - 888 - 824 - 4184 5.3 serial port mode 0 timing characteristics serial port mode 0 timing characteristics are illustrated in figure 17 and collected in table 2 0 . figure 17 . serial port mode 0 timing characteristics table 20 . serial port mode 0 timing characteristics symbol parameter minimum maximum units t xlxl txd clock period t (n +1) C ns t xlxh txd clock low to clock high (n > 1) 2t C 35 2t + 35 ns t xlxh txd clock low to clock high (n = 1) t C 35 t + 35 ns t xhxl txd clock high to clock low (n > 1) (n C 1) t C 35 (n C 1) t + 35 ns t xhxl txd clock high to clock low (n = 1) t C 35 t + 35 ns t qvxh rxd output data setup to txd clock high (n > 1) (n C 1) t C 35 C ns t qvxh rxd output data setup to txd clock high (n = 1) t C 35 C ns t xhqx rxd output data hold after txd clock high (n > 1) 2t C 35 C ns t xhqx rxd output data hold after txd clock high (n = 1) t C 35 C ns t xhqz rxd output data float after last txd clock h igh C t + 20 ns t dvxh rxd input data setup to txd clock high t + 20 C ns t xhdx rxd input data hold after txd clock high 0 C ns
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 59 of 85 1 - 888 - 824 - 4184 6. r eset operation the ia186eb/ia188eb will perform a reset operation any time the resin_n pin is active. figure 18 shows the reset sequence when power is applied to the ia186eb/ia188eb. an external clock connected to clkin must not exceed the v cc threshold being applied to the processor. this is normally not a problem if the clock driver is supplied with the same v cc that sup plies the processor. when attaching a crystal to the device, resin_n must remain active until both v cc and clkout are stable (the length of time is application - specific and depends on the startup characteristics of the crystal circuit). the resin_n pin i s designed to operate correctly using an rc reset circuit, but the designer must ensure that the ramp time for v cc is not so long that resin_n is never really sampled at a logic low level when v cc reaches minimum operating conditions. note: failure to ass ert resin_n while the device is powering up will result in unpredictable operation. figure 19 , warm reset timing, shows the timing sequence when resin_n is applied after v cc is stable and the device has been operating. any bus operation that is in progres s at the time resin_n is asserted will terminate immediately. while resin_n is active, bus signals lock_n, a19/once_n, and a18 C a16 are configured as inputs and weakly held high by internal pull - up transistors. only a19/ once_n can be overdriven to a low - to - enable once mode. 7. bus timing figures 18 through 26 on the following pages present the various bus cycles that are generated by the processor. t he figures show the relationship of the various bus signals to clkout. together with the information prese nt in ac characteristics , the figures allow the user to determine all the critical timing analysis needed for a given application.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 60 of 85 1 - 888 - 824 - 4184 figure 18 . cold reset timing
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 61 of 85 1 - 888 - 824 - 4184 figure 19 . warm reset timing
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 62 of 85 1 - 888 - 824 - 4184 fi gure 20 . read, fetch, and refresh cycle timing ad15 - ad0 (ia186eb); ad7 - ad0 (ia188eb) gcs7_n - gc s 0_n, lcs _ n, ucs _ n
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 63 of 85 1 - 888 - 824 - 4184 figure 21 . write cycle timing gcs7_n - gc s 0_n, lcs _ n, ucs _ n
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 64 of 85 1 - 888 - 824 - 4184 figure 22 . halt cycle timing
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 65 of 85 1 - 888 - 824 - 4184 figure 23 . interrupt acknowledge (inta1_n, inta0_n) cycle timing
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 66 of 85 1 - 888 - 824 - 4184 figure 24 . hold/hlda timing s 2 _ n C s 0 _ n a 1 9 / o n c e _ n , a 1 8 C a 1 6 b h e _ n ( i a 1 8 6 e b ) , r f s h _ n ( i a 1 8 8 e b ) g c s 7 _ n C g c s 0 _ n , u c s _ n , l c s _ n a d 1 5 C a d 0 ( i a 1 8 6 e b ) ; a 1 5 C a 8 , a d 7 C a d 0 ( i a 1 8 8 e b )
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 67 of 85 1 - 888 - 824 - 4184 figure 25 . refresh during hold acknowledge timing s 2 _ n C s 0 _ n a 1 9 / o n c e _ n , a 1 8 C a 1 6 b h e _ n ( i a 1 8 6 e b ) , r f s h _ n ( i a 1 8 8 e b ) p c s 6 _ n C p c s 0 _ n , m c s 3 _ n C m c s 0 _ n , l c s _ n , u c s _ n s 2 _ n C s 0 _ n a 1 9 / o n c e _ n , a 1 8 C a 1 6 w r _ n , l o c k _ n ; b h e _ n ( i a 1 8 6 e b ) ; r f s h _ n ( i a 1 8 8 e b ) g c s 7 _ n C g c s 0 _ n , u c s _ n , l c s _ n a d 1 5 C a d 0 ( i a 1 8 6 e b ) ; a 1 5 C a 8 , a d 7 C a d 0 ( i a 1 8 8 e b )
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 68 of 85 1 - 888 - 824 - 4184 figure 26 . ready timing
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 69 of 85 1 - 888 - 824 - 4184 8. instruction execution times ta ble 2 1 provides ia186eb and ia188eb execution times , mnemonic instruction, and additional information on execution, if required . the execution times apply to all versions of the parts. table 21 . instruction set timing instruction clock cycles comments ia186eb ia188eb aaa 3 3 C aad 6 6 C aam 40 40 C aas 3 3 C adc immediate to accumulator 1 1 C adc immediate to register/memory 3 13 C register/memory adc register/memory with register to either 1 /16 1/24 add immediate to a ccumulator 1 1 C add immediate to register/memory 1/ 19 1/32 register/memory add register/memory with register either 1/ 20 1/28 and immediate to accumulator 1 1 C and immediate to register/memory 1 /24 1/33 register/memory and register/memory and regis ter to either 1/ 12 1/15 bound 20/40 24/64 interrupt not taken/interrupt taken cbw 1 4 C clc 1 1 C cld 1 1 C cli 1 1 C cmc 2 2 C cmps 9 20 C cs 1 1 C cwd 1 1 C daa 4 4 C das 2 2 C dec register 1 1 C dec register/memory 1/24 1/32 register/memor y
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 70 of 85 1 - 888 - 824 - 4184 table 21 . instruction set timing (continued) instruction clock cycles comments ia186eb ia188eb div memory - byte 46 46 C C div register - byte 39 39 C div register - word 39 39 C idiv memory - byte 46 46 C idiv memory - word 49 51 C idiv register - byte 39 39 C idiv register - word 39 39 C imul immediate (signed) 5/24 5/33 register/memory imul memory - byte 4 20 C C C C C C n times) 8+8 n 16 + 16 n C C C C C jump not taken/jump taken jae 3/5 3/5 jb 3/5 3/5 jbe 3/5 3/5 jcxz 3/4 3/4 jump not taken/jump taken je 3/5 3/5 jump not taken/jump ta ken jg 3/5 3/5 jge 3/5 3/5 jl 3/5 3/5 jle 3/5 3/5 jmp direct intersegment 3 3 C C C jump not taken/jump taken jnae 3/5 3/5 jnb 3/5 3/5 jnbe 3/5 3/5 jne 3/5 3/5 jng 3/5 3/5 jnge 3/5 3/5 jnl 3/5 3/5 jnle 3/5 3/5 jno 3/5 3/5 jnp 3/5 3/5
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 71 of 85 1 - 888 - 824 - 4184 table 21 . instruction set timing (continued) instruction clock cycles comments ia186eb ia188eb jns 3/5 3/5 jump not taken/jump taken jnz 3/5 3/5 jo 3/5 3/5 jp 3/5 3/5 jpe 3/5 3/5 jpo 3/5 3/5 js 3/5 3/5 jz 3/5 3/5 lahf 2 2 C lds 1/24 1/33 register/memory lea 3 3 C leave 12 12 C les 12 32 C lock 1 1 C lods 8 12 C lods (repeated n times) 8+8 n 12 + 12 n C loop 3/4 3/4 loop not taken/loop taken loope 3/4 3/4 loop n ot taken/loop taken loopne 3/4 3/4 loopnz 3/4 3/4 loopz 3/4 3/4 mov accumulator to memory 5 8/12 8 - bit/16 - bit mov immediate to register 1 1 - mov immediate to register/memory 1/5 1/12 register/memory mov memory to accumulator 5 8/12 8 - bit/16 - bit mov register to register/memory 2/5 2/20 register/memory mov register/memory to register 2/5 2/20 mov register/memory to segment register 2/5 2/20 mov segment register to register/memory 2/5 2/20 movs 24 32 C movs (repeated n times) 24+24 n 32 + 32 n C mul memory - byte 16 20 C mul memory - word 15 25 C mul register - byte 5 5 C mul register - word 5 5 C neg 1/ 32 1/15 register/memory nop 1 1 C not 1/ 24 1/24 register/memory or immediate to accumulator 1 1 C
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 72 of 85 1 - 888 - 824 - 4184 table 21 . instruction set timing (continued ) instruction clock cycles comments ia186eb ia188eb or immediate to register/memory 1/ 32 1/32 register/memory or register/memory and register to either 1/ 32 1/24 out fixed port 5 8/12 8 - bit/16 - bit out variable port 5 12 C 8 - bit/16 - bit outs (repeated n times) 8+8 n 12/20 + 12/20 n 8 - bit/16 - bit pop memory 10 20 C C C C C C C C C C C C C C C register/memory rol register/memory by cl 1/ 8 1/16 rol register/memory by count 1/ 8 1/24 ror register/memory by 1 1/ 8 1/16 ror register/memory by cl 1/ 8 1/16 ror register/memory by count 1/ 8 1/24 sahf 2 2 C C register/memory sbb register/memory and register to either 1/ 11 1/40 register/memory scas 11 8/12 8 - bit/16 - bit scas (repeated n times) 11+8 n 8/12 +8 /12 n 8 - bit/16 - bit shl register/memory by 1 5 1/32 register/memory
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 73 of 85 1 - 888 - 824 - 4184 table 21 . instruction set tim ing (continued) instruction clock cycles comments ia186eb ia188eb shl register/memory by cl 1/ 20 1/24 register/memory shl register/memory by count 1/ 11 1/24 shr register/memory by 1 1/ 5 1/24 shr register/memory by cl 1/ 20 1/ 2 8 shr register/memor y by count 1/ 11 1/24 ss 1 1 C C - sub immediate from register/memory 1/ 11 1/28 register/memory sub register/memory and register to either 1/ 15 1/40 std 1 1 C C C C C register/memory test register/memory and register 1/ 12 1/20 register/memory wait 1 1 test_n = 0 xchg register with accumulator 2 2 C register/memory xlat 16 8 C C xor immediate to register/memory 1/ 11 1/32 register/memory xor register/memory and register to either 1/ 16 1/32 register/memory
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 74 of 85 1 - 888 - 824 - 4184 innovasic part number cros s - reference table s 2 2 through 2 4 cross - reference the innovasic part number with the corresponding intel part number . table 22 . innovasic part number cross - reference for the plcc innovasic part number intel part number package typ e temperature grades ia186ebplc84ir 2 lead free ( rohs - compliant ) ee80c186eb25 ee80c186eb20 en80c186eb25 en80c186eb20 en80c186eb13 n80c186eb25 n80c186eb20 n80c186eb13 tn80c186eb25 tn80c186eb20 tn80c186eb13 n80l186eb16 n80l186eb13 tn80l186eb16 tn80l186eb13 e n80l186eb13 84 - pin plcc commercial and i ndustrial ia188ebplc84ir 2 lead free ( rohs - compliant ) ee80c188eb25 ee80c188eb20 ee80c188eb13 en80c188eb25 en80c188eb20 en80c188eb13 n80c188eb25 n80c188eb20 n80c188eb13 tn80c188eb25 tn80c188eb20 tn80c188eb13 ee80l188e b16 en80l188eb13 n80l188eb16 n80l188eb13 tn80l188eb16 tn80l188eb13 84 - pin plcc commercial and i ndustrial
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 75 of 85 1 - 888 - 824 - 4184 table 23 . innovasic part number cross - reference for the pqfp innovasic part number intel part number package type temperatu re grades ia186ebpqf80ir 2 lead free ( rohs - compliant ) EG80C186EB25 es80c186eb20 es80c186eb13 s80c186eb25 s80c186eb20 s80c186eb13 ts80c186eb25 ts80c186eb20 ts80c186eb13 eg80l186eb16 eg80l186eb13 s80l186eb16 s80l186eb13 ts80l186eb16 ts80l186eb13 80 - pin pqfp commercial and i ndustrial ia188ebpqf80ir 2 lead free ( rohs - compliant ) eg80c188eb25 es80c188eb20 s80c188eb25 s80c188eb20 s80c188eb13 ts80c188eb25 ts80c188eb20 ts80c188eb13 es80l188eb13 ts80l188eb16 ts80l188eb13 80 - pin p qfp commercial and industrial
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 76 of 85 1 - 888 - 824 - 4184 table 24 . innovasic part number cross - reference for the lqfp innovasic part number intel part number package type temperature grades ia186ebplq80ir 2 lead free ( rohs - compliant ) yw80c186eb25 yw80c186eb20 sb80c186eb25 sb80c186eb20 sb80c18 6eb13 yw80l186eb16 yw80l186eb13 sb80l186eb16 sb80l186eb13 80 - pin lqfp commercial and i ndustrial ia188ebplq80ir 2 lead free ( rohs - compliant ) yw80c188eb25 yw80c188eb20 sb80c188eb25 sb80c188eb20 sb80c188eb13 yw80l188eb16 yw80l188eb13 sb80l188eb16 sb80l188eb13 80 - pin lqfp commercial and i ndustrial
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 77 of 85 1 - 888 - 824 - 4184 9. errata the following errata are associated with version 0 of the ia186eb/ia188eb. a workaround to the identified problem has been provided where possible. 9.1 summary table 25 presents a summary of errata. table 25 . summary of errata errata no. problem ver. 0 ver. 2 1 alternate mode (txcon[1] == 1) for timer 0 and 1 has some functional issues. exists fixed 2 when the extension byte (mod field) is set to D11, some instructions will cau se the cpu to hang. exists fixed 3 when the chip is put in sfnm mode for int0 or int1, the lvl bit is automatically set for those interrupts. exists fixed 4 timer 2 will stop or not start counting. exists fixed 5 write does not occur when counter is a ctively counting. exists fixed 6 program counter can become corrupted if an interrupt occurs. exists fixed 7 bound instruction uses bad data when index addresses are on odd boundary in memory. exists fixed 8 pin lock_n does not have an internal pullup a nd will float during reset and bus hold. exists exists 9 the relocation register (relreg, pcb offset 0xa8) can only be modified by an 8 - bit write. exists exists 10 when the timer compare register for any of the timers is set to x0000, the max count is xffff instead of x10000 as in the oem part. exists exists 11 nmi cannot bring chip out of powerdown mode. - exists
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 78 of 85 1 - 888 - 824 - 4184 errata no. problem ver. 0 ver. 2 12 illegal serial port modes do not match oem part. exists exists 13 non - maskable interrupt (nmi) can be pre - empted by maskable interrupt. exists exists 14 ready signal may not be recognized in bus cycles with zero wait states . exists exists 9.2 detail errata no. 1 problem: alternate mode (txcon[1] == 1) for timer 0 and 1 has some functional issues. description: txout will co ntinuously toggle at 1/2 clkout regardless of count register values. the maxcount compare will not work. the live count will compare against txcmpa and txcmpb in alternate cycles. this could cause a compare (and the associated interrupt, or switch the intended compare, or stop counting altogether) to occur early or not at all. the txout pin may start in the wrong state if the user writes to txcon register bit [12]. when in retrigger mode, timer 1 will not function correctly. input pulses on t0in will cause counter to begin counting. workaround: none.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 79 of 85 1 - 888 - 824 - 4184 errata no. 2 problem: when the extension byte (mod field) is set to D11, some instructions will cause the cpu to hang. description: although there are faster versi ons of each instruction (these are not commonly used by compilers), the following instructions will cause the cpu to hang when the extension byte (mod field) is set to D11 : 8d (lea) 8f (pop memory) c6 (mov immediate8 to memory/register) c7 (mov immediate1 6 to memory/register) fe (push memory) ff (push memory) workaround: substitute instruction s in the following table. instruction workaround 8d (lea) use mov register (89 or 8b) 8f (pop memory) use pop register (0101_0xxx) c6 (mov immediate8 to memory/ register) use mov immediate8 to register (1011_0xxx) c7 (mov immediate16 to memory/register) use mov immediate16 to register (1011_1xxx) fe (push memory) use push register (0101_0xxx) ff (push memory) use push register (0101_0xxx) errata no. 3 problem: when the chip is put in sfnm mode for int0 or int1, the lvl bit is automatically set for those interrupts. workaround: none.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 80 of 85 1 - 888 - 824 - 4184 errata no. 4 problem: timer 2 will stop or not start counting. description: writing a logic D1 to unused bits in the timer control register can cause the timer to stop counting or to never start counting. workaround: do not write a logic D1 to any unused or reserved bits in the timer control register. errata no. 5 problem: write does not occur when counter is actively counting . description: if a timer incremented its count register to the currently active compare register during a write to that count register, the write would not occur . workaround: do not write count regi ster while that counter is actively counting . errata no. 6 problem: program counter can become corrupted if an interrupt occurs . description: if an interrupt occurs during the decode stage of a test instruction using an opcode of the form 1111_0111_1100_ 0xxx, the program counter could become corrupted upon returning from the interrupt handler . workaround: none . errata no. 7 problem: bound instruction uses bad data when index addresses are on odd boundary in memory . description: bound instruction will use bad data if index address lsb is a D1 in memory . workaround: none .
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 81 of 85 1 - 888 - 824 - 4184 errata no. 8 problem: pin lock_n does not have an internal pullup . description: because pin lock_n does not have an internal pullup , it will float during reset and bus hold . wo rkaround: an external pullup may be necessary if there is high external load on the signal. errata no. 9 problem: the relocation register (relreg, pcb offset 0xa8) can only be modified by an 8 - bit write. description: the relocation register (relreg, p cb offset 0xa8) can only be modified by an 8 - bit write. a 16 - bit write will have no effect. the 186 eb is unaffected. workaround: use an 8 - bit access to affect the relreg register. errata no. 10 problem: when the timer compare register for any of the t imers is set to x0000, the max count is xffff instead of x10000 as in the oem part. description: the timer output will change one count earlier than it should when the max count is set to x0000. workaround: the workaround is application dependent. pl ease contact innovasic technical support if this erratum is an issue . errata no. 11 problem: nmi cannot bring chip out of powerdown mode. description: only a reset brings the part out of powerdown after a hlt instruction is executed with the pwrdn bit set in the pwrcon register. workaround: use idle instead of pwrdn.
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 82 of 85 1 - 888 - 824 - 4184 errata no. 12 problem: illegal serial port modes do not match oem part. description: if the mode bits of the serial control register (s1con, s0con) are set to an illegal encoding (0x5 , 0x6, or 0x7), the innovasic part acts as though it were in mode 4. the oem part acts as if it were in mode 1. workaround: use a valid encoding for serial mode. errata no. 13 problem: non - maskable interrupt (nmi) can be pre - empted by maskable interru pt. description: when instruction execution unit is in decode state for 2 or more consecutive cycles and an nmi is recognized, it could be pre - empted by a maskable interrupt. workaround: none. errata no. 14 problem: ready signal may not be recognized i n bus cycles with zero wait states . description: when a chip select is set to use the ready signal to extend a bus cycle that normally has no wait states (start register bits 3 - 0 == 0000), the ready signal may not be recognized in time to extend the bus c ycle. workaround: set wait states to 1 or more if using ready to extend bus cycles .
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 83 of 85 1 - 888 - 824 - 4184 revision history table 2 6 presents the sequence of revisions to document ia 211080 3 14 . table 26 . revision history date revision description page (s) july 30, 2008 0 0 first edition released . na october 13 , 2008 01 pin number range Dad15 C a8 corrected to Da15 C a8 in figures 26 and 27. errata no. 4 added. [also cover page, header, footer, and errata chapter reformatted to meet publication stand ards.] 66, 67, 78, 79, 80, 81 january 14, 2009 02 updated errata table for version 00 C added 3 errata (#5 C 7) . 81, 83 march 29 , 2009 03 updated instruction set timing for 186eb; changed 188eb column to tbd pending completion of new tests ; updated table 9 ratings; updated table 11 parameters and ratings; removed figures 16 and 17, and reordered subsequent figures; updates table 18 ratings and notes; updated table 19 parameters, ratings and notes. 42, 43, 55, 56, 68 - 72 april 24, 2009 04 ad ded availability of a non - rohs compliant version of the 188eb in the 80 - pin lqfp package. added two errata for version 2 of the device . noted that all other errata have been fixed in version 2. 75, 76, 79 may 5, 2009 05 noted the test conditions used to derive the values in tables 13 - 16; noted that the instruction set timing in table 21 appli es to all versions of the parts . 51, 68 may 1 8 , 2009 06 updated figures 4, 5 and 10. updated tables 3, 4, 6, 7, 8, 12. updated table 21 to provide revised instruc tion set timing for the 186eb and to add instruction set timing for the 188eb, based on the most recent test results. 15 - 18, 23, 25 - 41, 45, 48, 50, 68 - 72 june 4, 2009 07 updated v oh parameter on table 11; corrected labels on figures 20 - 21 ; added errata 10 . 43, 61, 62 , 80
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 84 of 85 1 - 888 - 824 - 4184 date revision description page (s) september 4, 2009 08 added a note to table 12 regarding the step id register. 50 february 25, 2011 09 elimination of pages with snpb lead plating options 74 - 76 march 23, 2011 10 updated instruction set timing table to incorporate div an d idiv values. 70 june 12, 2011 11 added errata 11 and 12. 77, 78, 81 july 5, 2011 12 added errata 13. 7 8 , 82 july 10, 2011 13 added errata 14. 78, 82
ia186eb/ia188eb data sheet 8 - bit/16 - bit microcontrollers july 10 , 2011 ia211080314 - 1 3 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 85 of 85 1 - 888 - 824 - 4184 10. for additional information the innovasic semiconductor ia186eb and ia188eb microcontrollers are f orm, fit, and function replacements for the original intel ? 80c186eb, 80c188eb, 80l186eb, and 80l188eb 16 - bit high - integration embedded processors. the innovasic support team wants our information to be complete, accurate, useful, and easy to understand. please feel free to contact our experts at innovasic at any time with suggestions, comments, or questions. innovasic support team 3737 princeton ne suite 130 albuquerque, nm 87107 (505) 883 - 5263 fax: (505) 883 - 5477 toll free: (888) 824 - 4184 e - mail: support@innovasic.com website: http://www.innovasic.com

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